In very large scale integration (VLSI) technology, the complexity of modern system on chip (SOC) designs is increasing day by day where different parts of the system, some of which are analog in nature and some of which are digital in nature, are integrated on a single chip. In such an SOC design, it is common for different parts of the chip to operate with different supply voltages. For example, a core digital circuit may operate with a first supply voltage at 1.6V while a periphery input/output circuit may operate with a second supply voltage at 2.6V. This is just an example, and it will be understood that many SOC designs could use three or more different supply voltages, and further to that, very high voltages in excess of 10V may be required. So, for effective operation of the SOC design, there is a need to interact between the different parts of the SOC working at different supply voltages. A level shifter is a circuit which converts the logic signals from one voltage level to another voltage level as the logic signals cross between circuits operating with different supply voltages. This requires a level shifting of the logic signals.
Reference is made to FIG. 1 showing a circuit diagram for a conventional level shifting circuit 10 operable to convert logic signals between a first supply voltage (having a high supply node VLOW and a low supply node GND) and a second supply voltage (having a high supply node VHIGH and a low supply node GND). The circuit shown in FIG. 1 represents a conventional positive level shifter. The level shifting circuit 10 comprises four transistors (M0, M1, M2 and M3) and one inverter 12. The inverter 12 functions to generate a complementary input signal INN from the received input signal IN. The inverter is powered from the first supply voltage VLOW. The transistors M0 and M1 are n-channel MOSFET devices with gate (control) terminals coupled to receive the complementary input signals IN and INN. Source (conduction) terminals of the transistors M0 and M1 are coupled to the ground node GND. Drain (conduction) terminals of the transistors M0 and M1 are coupled to output nodes of the level shifter 10 producing the complementary output signals OUTN and OUT. The transistors M2 and M3 are p-channel MOSFET devices having gate (control) terminals cross-coupled in a latching circuit to the output nodes of the level shifter. Drain (conduction) terminals of the transistors M2 and M3 are coupled to the output nodes of the level shifter 10 producing the complementary output signals OUTN and OUT. Source (conduction) terminals of the transistors M0 and M1 are coupled to the high supply voltage VHIGH. With the two different supply voltages VLOW and VHIGH, an input signal IN with a logic high voltage at the VLOW voltage level is converted to an output signal (in this case having a complementary signal form with signals OUT and OUTN) with a logic high voltage at the high supply voltage VHIGH for the signal OUT and a logic low voltage at the high supply voltage VHIGH for the signal OUTN.
The following Table summarizes operation of the circuit 10:
TABLE 1InputOutputINOUTOUTNVLOWVHIGH0 v0 v0 vVHIGH
A problem with the level shifting circuit 10 of FIG. 1 is that if VHIGH is of a very high voltage level which is more than the safe operating region of transistors used, then all the transistors will be stressed and there will be reliability issues in the circuit. So, to reduce the voltage stress at each transistor it is known in the art to use different circuits or topologies for level shifting.
One example of such a different circuit or topology is shown in FIGS. 2A-2D. Here, four separate level shifting circuits 20, 22, 24 and 26 are coupled in cascade with each other. The overall level shifting circuit is accordingly a four stage level shifter that is configured to provide higher voltage swings (for example, two times more than the safe operating voltage of the transistors or devices). There are different supply voltages for each level shifting stage. Thus, for a four stage circuit there are eight different supply voltages to achieve the desired level shifting functionality.
The first level shifting circuit stage 20 has a circuit configuration like the circuit 10 of FIG. 1. In the first stage, the input signal IN is converted from logic high voltage VLOW1 to a logic high voltage VMID1 for the output signal OUT1. The complementary output signals OUT1 and OUTN1 accordingly vary from 0V (GND) to VMID1 and vice versa depending upon the state of the input signal IN voltage level. These signals OUT1 and OUTN1 are then fed to the next level shifting circuit stage 22 as input signals.
The second level shifting circuit stage 22 comprises six transistors (M4, M5, M6, M7, M8 and M9). The pair of transistors M4 and M5 are n-channel MOSFET devices with gate terminals coupled to receive the complementary input signals which are the complementary output signals OUT1 and OUTN1 from the first stage 20. Source terminals of the transistors M4 and M5 are coupled to a low supply voltage VLOW2. Drain terminals of the transistors M4 and M5 are coupled to source terminals of a pair of transistors M6 and M7 which comprise cascode devices. The gate terminals of cascode transistors M6 and M7 are coupled to receive the high supply voltage VMID1 for the first stage 20. Drain terminals of the transistors M6 and M7 are coupled to output nodes of the level shifter 22 producing the complementary output signals OUTN2 and OUT2. The pair of transistors M8 and M9 are p-channel MOSFET devices having gate terminals cross-coupled in a latching circuit to the output nodes of the level shifter 22. Drain terminals of the transistors M8 and M9 are coupled to the output nodes of the level shifter 22. Source terminals of the transistors M8 and M9 are coupled to the high supply voltage VMID2. The output nodes OUT2 and OUTN2 of the second stage 22 change their state either from VLOW2 to VMID2 level or reciprocally depending upon the logic state of the received input signals which are output from first stage 20.
The VLOW2 voltage level in the second stage 22 is set in such a way that a difference between the VMID2 and VLOW2 voltage does not exceed a safe operation region of the transistors M4-M9.
The third level shifting circuit stage 24 likewise comprises six transistors (M10, M11, M12, M13, M14 and M15) connected in the same circuit configuration as stage 22. However, the stage 24 is coupled to a high supply voltage VMID3 and low supply voltage VLOW3). The inputs to stage 24 are coupled to the outputs of stage 22. Additionally, the gates of the cascode transistors M12 and M13 of the stage 24 are coupled to receive the high supply voltage VMID2 for the second stage 22.
The VLOW3 voltage level in the third stage 24 is set in such a way that a difference between the VMID3 and VLOW3 voltage does not exceed a safe operation region of the transistors M10-M15.
The fourth level shifting circuit stage 26 likewise comprises six transistors (M16, M17, M18, M19, M20 and M21) connected in the same circuit configuration as stages 22 and 24. However, the stage 26 is coupled to a high supply voltage VMID4 and a low supply voltage VLOW4. The inputs to stage 26 are coupled to the outputs of stage 24. Additionally, the gates of the cascode transistors M18 and M19 of the stage 26 are coupled to receive the high supply voltage VMID3 for the third stage 24.
The VLOW4 voltage level in the fourth stage 26 is set in such a way that a difference between the VMID4 and VLOW4 voltage does not exceed a safe operation region of the transistors M16-M21.
The level shifting circuit of FIGS. 2A-2D accordingly functions to level shift the input signal IN from the high supply voltage VLOW1 (referenced to ground) to the high supply voltage VMID1 (also referenced to ground) (using stage 20), then shift to a high supply voltage VMID2 referenced to a low supply voltage VLOW2 (using stage 22), then shift to a high supply voltage VMID3 reference to a low supply voltage VLOW3 (using stage 24), and then shift to a high supply voltage VMID4 reference to a low supply voltage VLOW4 (using stage 26). The following Tables summarize operation of the circuit 20:
TABLE 21st stageInputOutputININNOUT1OUTN1VLOW10 vVMID10 v0 vVLOW10 vVMID1
TABLE 32nd stageInputOutputOUT1OUTN1OUT2OUTN2VMID10 vVMID2VLOW20 vVMID1VLOW2VMID2
TABLE 43rd stageInputOutputOUT2OUTN2OUT3OUTN3VMID2VLOW2VMID3VLOW3VLOW2VMID2VLOW3VMID3
TABLE 54th stageInputOutputOUT3OUTN3OUT4OUTN4VMID3VLOW3VMID4VLOW4VLOW3VMID3VLOW4VMID4
The transistors M6, M7, M12, M13, M18 and M19 are positioned in cascoded fashion to isolate the NMOS input transistors M4, M5, M10, M11, M16 and M17 from the respective output nodes when the output signal levels goes to its maximum logic high value for the given supply voltage.
A drawback of multi-stage level shifters (such as shown in FIGS. 2A-2D) is that the circuit requires many different supply voltages in order to obtain a swing of twice the maximum operating voltage of the transistors used. Also, these supply voltages should be chosen in such a way that none of the transistors is placed under voltage stress.
For example, if a 4.5V capable transistor is used and it is desired to achieve a VMID4=VHIGH=13.5V, then following voltages should be selected for the various supply voltages:
First stage: input signal logic high voltage 1.8 v and logic low voltage (GND) 0V, with high supply voltage VMID1=4.5V;
Second stage: VMID2=7.5V; VLOW2=3V;
Third stage: VMID3=10.5V; VLOW3=6V; and
Fourth stage: VMID4=13.5V; VLOW4=9V.
The difference between|VMID(n)−VLOW(n+1)|min==1.5V, where n>=1in order to allow proper operation of the level shifter stages.
An additional drawback of multi-stage level shifters is the requirement of many supply voltages (high and low) for the stages, and it is known in the art that provision of the supply voltage circuitry for such supply voltages may not be easily available and if available this comes with a larger cost in terms of both area and power. So, the need for the many supply voltages in multi-stage level shifters puts a constraint on practical use of this type of level shifting circuit. Still further, the foregoing problems are magnified if the system requires even higher levels for the voltage swings.
A still further drawback is that the generated output signals do not include logic signals which vary between, for example, “VMID2 to 0 v”, “VLOW4 to 0 v” or “VLOW4 to VMID1”. That is from “7.5 v to 0 v”, “9 v to 0 v” or “9 v to 4.5 v”. So, if there is a situation where such a signal varying between these supply levels is needed, then the multi-stage level shifting circuit is not usable.
Additionally, there is a further concern with switching speed. Multi-stage level shifting circuits will exhibit a slower switching speed than other types of level shifters, especially those which operate using only a single stage. Thus, it would be preferable to use a single stage. FIG. 3 shows an example of a single stage level shifting circuit 60 operable to convert a logic signal having a high supply voltage VLOW referenced to ground GND to a plurality of different output supply voltages.
The circuit 60 shown in FIG. 3 is known as a single stage cascoded voltage level shifter. This circuit uses four supply voltages referred to as VLOW, VMIDL, VMIDH and VHIGH referenced to a ground voltage GND. The input signal IN has a logic high voltage level at the VLOW supply voltage level. The supply voltages VMIDL and VMIDH are used as cascode voltages for biasing the gate terminals of cascode transistors in the circuit 60. The supply voltage VHIGH is the level shifted output voltage, and thus the output signal OUTH has a logic high voltage level at the VHIGH supply voltage level. The circuit 60 supports a maximum voltage swing that is three-times the maximum operating voltage of the transistors and it is fully cascoded by the VMIDL and VMIDH voltages to avoid voltage stress in the devices. This circuit 60 further addresses most of the problems associated with the multi-stage level shifter circuits.
The level shifting circuit 60 comprises twelve transistors (M0-M11) and one inverter 62. The inverter 62 functions to generate a complementary input signal INN from the received input signal IN. The inverter is powered from the high supply voltage VLOW referenced to ground GND. The pair of input transistors M0 and M1 are n-channel MOSFET devices with gate (control) terminals coupled to respectively receive the complementary input signals IN and INN. Source (conduction) terminals of the transistors M0 and M1 are coupled to the ground node GND. Drain (conduction) terminals of the transistors M0 and M1 are coupled, respectively, to a pair of intermediate nodes NET2 and NET1. The intermediate nodes NET2 and NET1 of the circuit 60 change their state either from ground to VMIDL−|Vtn| or reciprocally depending upon the logic state of the received input signal IN (where Vtn is the threshold voltage of the NMOS transistors M2 and M3).
The pair of transistors M2 and M3 are coupled, respectively, in series with transistors M0 and M1 at the intermediate nodes NET2 and NET1 with the source terminals of transistors M2 and M3 coupled, respectively, to the drain terminals of transistors M0 and M1. The gate terminals of cascode transistors M2 and M3 are coupled to receive the low cascode supply voltage VMIDL. Drain terminals of the transistors M2 and M3 are coupled, respectively, to a complementary pair of output nodes OUTNL and OUTL. The transistors M2 and M3 are n-channel MOSFET devices. The output nodes OUTNL and OUTL of the circuit 60 change their state either from ground to MIDH−|Vtn| or reciprocally depending upon the logic state of the received input signal IN (where Vtn is the threshold voltage of the NMOS transistors M6 and M7).
The pair of transistors M4 and M5 are coupled, respectively, in series with transistors M2 and M3 at the output nodes OUTNL and OUTL with the drain terminals of transistors M4 and M5 coupled, respectively, to the drain terminals of transistors M2 and M3. The gate terminals of cascode transistors M4 and M5 are coupled to receive the low cascode supply voltage VMIDL. Source terminals of the transistors M4 and M5 are coupled, respectively, to the pair of intermediate nodes NET3 and NET4. The transistors M4 and M5 are p-channel MOSFET devices. The intermediate nodes NET3 and NET4 of the circuit 60 change their state either from VMIDL+|Vtp| to VMIDH−|Vtn| level or reciprocally depending upon the logic state of the received input signal IN (where Vtp is the threshold voltage of the PMOS transistors M4 and M5 and Vtn is the threshold voltage of the NMOS transistors M6 and M7).
The pair of transistors M6 and M7 are coupled, respectively, in series with transistors M4 and M5 at the intermediate nodes NET3 and NET4 with the source terminals of transistors M6 and M7 coupled, respectively, to the source terminals of transistors M4 and M5. The gate terminals of cascode transistors M6 and M7 are coupled to receive the high cascode supply voltage VMIDH. Drain terminals of the transistors M6 and M7 are coupled, respectively, to the pair of complementary output nodes OUTNM and OUTM. The transistors M6 and M7 are n-channel MOSFET devices. The output nodes OUTNM and OUTM of the circuit 60 change their state either from VMIDL+|Vtp| to VHIGH level or reciprocally depending upon the logic state of the received input signal IN (where Vtp is the threshold voltage of the PMOS transistors M4 and M5).
The pair of transistors M8 and M9 are coupled, respectively, in series with transistors M6 and M7 at the output nodes OUTNM and OUTM with the drain terminals of transistors M8 and M9 coupled, respectively, to the drain terminals of transistors M6 and M7. The gate terminals of cascode transistors M8 and M9 are coupled to receive the high cascode supply voltage VMIDH. Source terminals of the transistors M8 and M9 are coupled, respectively, to the pair of complementary output nodes OUTNH and OUTH. The transistors M8 and M9 are p-channel MOSFET devices.
The pair of transistors M10 and M11 are p-channel MOSFET devices having gate terminals cross-coupled in a latching circuit to the output nodes OUTNH and OUTH. Drain terminals of the transistors M10 and M11 are coupled, respectively, to the output nodes OUTNH and OUTH. Source terminals of the transistors M10 and M11 are coupled to the high supply voltage VHIGH. The output nodes OUTNH and OUTH of the circuit 60 change their state either from VMIDH+|Vtp| to VHIGH level or reciprocally depending upon the logic state of the received input signal IN (where Vtp is the threshold voltage of the PMOS transistors M8 and M9).
The following Tables summarize operation of the circuit 60:
TABLE 6InputOutputININNOUTHOUTMNET4OUTLNET1VLOW0vVHIGHVHIGHVMIDH−|Vtn|VMIDH−|Vtn|VMIDL−|Vtn|0vVLOWVMIDH+|Vtp|VMIDL+|Vtp|VMIDL +|Vtp|00
TABLE 7InputOutputININNOUTNHOUTNMNET3OUTNLNET2VLOW0vVMIDH+|Vtp|VMIDL+|Vtp|VMIDL+|Vtp|000vVLOWVHIGHVHIGHVMIDH−|Vtn|VMIDH−|Vtn|VMIDL−|Vtn|
As noted above, the voltages at a number of nodes settle either to a voltage of VMID+|Vtp| or VMID−|Vtn|, where |Vtp| is the threshold voltage of the PMOS transistors and |Vtn| is the threshold of the NMOS transistors. These threshold voltages are known to vary according to the different process corners and temperature. So, the output voltage levels which are driven at these nodes are not stable and are poorly driven.
Moreover, if in case the voltage at one of the output nodes changes due to coupling or charge loss, for example when IN is at 0V the minimum voltage at OUTH node is VMIDH+|Vtp|, and if by any means it goes below that voltage then there is no circuitry to pull that node to its desired state leading to improper functionality.
A further problem with the level shifting circuit 60 is that the switching speed of the circuit slows when driving a load from nodes OUTH and OUTHN. This is because the minimum voltage at OUTH and OUTHN nodes (i.e., VMIDH+|Vtp|) is not very well driven. So, when a capacitive load is driven, charging and discharging of capacitive load takes a longer time.
There is accordingly a need in the art for an improved level shifting circuit that addresses the drawbacks of prior art circuit such as those shown in FIGS. 1, 2A-2D and 3.